1. Field of the Invention
The present invention relates to a switching system processor, and more particularly, to a duplexing structure of a switching system processor and its method.
2. Background of the Related Art
In general, a switching system includes a plurality of processors, which are required to process data on a real time basis, and are managed by a duplexing channel to prevent an interruption in processing of data, even when a malfunction occurs. A duplexing channel is generally formed through a back plane between two processor boards having the same construction, so that while one processor is operating in an active mode, the other processor is operating in a standby mode. When a disturbance occurs at the active mode processor, the standby mode processor is switched to an active mode to successively perform the data processing.
FIG. 1 shows a duplexing structure of a background art switching system processor. In this drawing, two processors 10 and 20, for implementing an actual duplexing operation have similar construction, and a duplexing channel is formed through a back plane. A requisite portion for a duplexing operation of the two processors 10 and 20 are shown in FIG. 1 illustrating a case where the first processor 10 is operating in an active mode while the second processor 20 is operating in a standby mode. A description and a drawing for the opposite case are omitted.
The first processor 10, the active mode processor, includes a microprocessor 11, a duplexing controller 12, an address FIFO 13, an address buffer 14, a data buffer 15, a data FIFO 16, a memory controller 17 and a memory 18. The second processor 20, the standby mode processor, includes a microprocessor 21, a bus arbitration unit 22, an address buffer 23, a data buffer 24, a memory controller 25 and a memory 26.
If use of a processor bus of the second processor 20 is required while the microprocessor 11 is reading or writing data, the duplexing controller 12 requests use of the bus from the bus arbitration unit 22 and controls the address FIFO 13, the data FIFO 16, the address buffer 14 and the data buffer 15, for transmitting the address and the data signals.
When the microprocessor 11 performs a concurrent writing operation into the memories 18 and 26 under the control of the duplexing controller 12, the address FIFO 13 and the data FIFO 16 temporarily store the address and the data.
The address buffers 14 and 23 and the data buffers 15 and 24 offer a transfer path for the address and the data signal, respectively, when the data is read from or written into the memory 26 of the second processor 20.
At the request for use of the bus by the duplexing controller 12, the bus arbitration unit 22 monitors use of the bus by the microprocessor 21, arbitrates the use of the bus between the displaying controller 12 and the microprocessor 21, and controls the address buffer 23 and the data buffer 24.
If the microprocessor 11 of the first processor 10 is intended to read the data stored in the memory 26 of the second processor 20, the duplexing controller 12 requests use of the bus from the bus arbitration unit 22. Upon authorization from the bus arbitration unit 22, the duplexing controller 12 and the bus arbitration unit 22 control the address buffers 14 and 23, respectively, to offer a transfer path for the address signal, read a data from a corresponding address of the memory 26 and transfer the data to the microprocessor 11 through the data buffers 24 and 15.
If the microprocessor 11 writes a data into the memory 26, the duplexing controller 12 requests use of the bus from the bus arbitration unit 22. Upon authorization, the duplexing controller 12 and the bus arbitration unit 22 control the address buffers 14 and 23 and the data buffers 15 and 24, respectively, to offer a transfer path for the address and the data, through which the data is written into a corresponding address of the memory 26.
If the microprocessor 11 is intending to concurrently write a data into both of the memories 18 and 26, that is, the data carried on the address signal outputted from the microprocessor 11 is a data to be duplexed, then data writing is performed into the memory 18 through the memory controller 17, and simultaneously, the data is temporarily stored in the data FIFO 16, and its address signal is temporarily stored in the address FIFO 13 under the control of the duplexing controller 12.
If a request by the duplexing controller 12 for use of the bus from the bus arbitration unit 22 is allowed, the address signal and the data stored in the address FIFO 13 and the data FIFO 16 are written into the memory 26 through the address buffer 23 and the data buffer 24.
Regarding the duplexing structure of the background art switching system processor, since the duplexing channel between the active mode processor 10 and the standby mode processor 20 is only separated from the processor bus by the address buffer 23 and the data buffer 24 in the standby mode processor 20, the actual clock speed of the duplexing channel must be the same as the actual clock speed of the processor bus. However, since the duplexing of the switching system processor is made through the back plane, if the clock signal of the duplexing channel formed through the back plane is of high frequency, the phases of the signals transmitted between the two processors may not be identical.
Therefore, for a high-performance microprocessor requiring a higher speed processor bus clock, since the clock speed of the duplexing channel formed between the dual processors hardly meets the speed of the bus clock of the higher speed processor, there occurs a problem in that the high-performance microprocessor is limited in use with such a duplexing structure of the background art.
An object of the invention is to solve at least the above problems and/or disadvantages and to provide at least the advantages described hereinafter.
Another object of the present invention is to provide a duplexing structure of a switching system processor.
Another object of the present invention is to implement a duplexing channel using an independent clock.
Another object of the present invention is to form a duplexing channel.
Another object of the present invention is to implement a duplexing operation in an active mode and a standby mode.
The object of the present invention can be obtained, as a whole or in parts, by a duplexing structure of a switching system processor having first and second processor boards for which a duplexing channel is formed through a back plane and is dually operated in an active mode and in a standby mode, wherein each processor bus connected to a microprocessor of a processor board at one side and a duplexing channel connected to a processor board at the other side use different clocks so that the two processor boards are independently operated.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.